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<title>CMSIS-Core (Cortex-M): PMU Events for Armv8.1-M</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.4.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">PMU Events for Armv8.1-M<div class="ingroups"><a class="el" href="group__pmu8__functions.html">PMU Functions for Armv8.1-M</a></div></div>  </div>
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<div class="contents">

<p>IDs for Armv8.1-M architecture defined events.  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6e02b08550d7e9b273ff7913f1b57bea">ARM_PMU_SW_INCR</a>&#160;&#160;&#160;0x0000</td></tr>
<tr class="memdesc:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software update to the PMU_SWINC register, architecturally executed and condition code check pass.  <a href="#ga6e02b08550d7e9b273ff7913f1b57bea">More...</a><br/></td></tr>
<tr class="separator:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac43e0e0f9e385ea66402bdeebf3fea3e">ARM_PMU_L1I_CACHE_REFILL</a>&#160;&#160;&#160;0x0001</td></tr>
<tr class="memdesc:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">L1 I-Cache refill.  <a href="#gac43e0e0f9e385ea66402bdeebf3fea3e">More...</a><br/></td></tr>
<tr class="separator:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">ARM_PMU_L1D_CACHE_REFILL</a>&#160;&#160;&#160;0x0003</td></tr>
<tr class="memdesc:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="mdescLeft">&#160;</td><td class="mdescRight">L1 D-Cache refill.  <a href="#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">More...</a><br/></td></tr>
<tr class="separator:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7505ae74c1d905f01b05dd5466c1efc0">ARM_PMU_L1D_CACHE</a>&#160;&#160;&#160;0x0004</td></tr>
<tr class="memdesc:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">L1 D-Cache access.  <a href="#ga7505ae74c1d905f01b05dd5466c1efc0">More...</a><br/></td></tr>
<tr class="separator:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2e8725ee07c2b2c75a1b54261bc26cc8">ARM_PMU_LD_RETIRED</a>&#160;&#160;&#160;0x0006</td></tr>
<tr class="memdesc:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory-reading instruction architecturally executed and condition code check pass.  <a href="#ga2e8725ee07c2b2c75a1b54261bc26cc8">More...</a><br/></td></tr>
<tr class="separator:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8179d1144f8ec993bd1343e276d7b49b">ARM_PMU_ST_RETIRED</a>&#160;&#160;&#160;0x0007</td></tr>
<tr class="memdesc:ga8179d1144f8ec993bd1343e276d7b49b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory-writing instruction architecturally executed and condition code check pass.  <a href="#ga8179d1144f8ec993bd1343e276d7b49b">More...</a><br/></td></tr>
<tr class="separator:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">ARM_PMU_INST_RETIRED</a>&#160;&#160;&#160;0x0008</td></tr>
<tr class="memdesc:ga8a5e60eee460addfc66e275a2c4c4800"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction architecturally executed.  <a href="#ga8a5e60eee460addfc66e275a2c4c4800">More...</a><br/></td></tr>
<tr class="separator:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac97858bd621eab4592569444f0a5c37f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f">ARM_PMU_EXC_TAKEN</a>&#160;&#160;&#160;0x0009</td></tr>
<tr class="memdesc:gac97858bd621eab4592569444f0a5c37f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Exception entry.  <a href="#gac97858bd621eab4592569444f0a5c37f">More...</a><br/></td></tr>
<tr class="separator:gac97858bd621eab4592569444f0a5c37f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8">ARM_PMU_EXC_RETURN</a>&#160;&#160;&#160;0x000A</td></tr>
<tr class="memdesc:gaf9424157e9c5dca3a3689d181005c4f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Exception return instruction architecturally executed and the condition code check pass.  <a href="#gaf9424157e9c5dca3a3689d181005c4f8">More...</a><br/></td></tr>
<tr class="separator:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54fd2c392399221077c67866a395e587"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga54fd2c392399221077c67866a395e587">ARM_PMU_PC_WRITE_RETIRED</a>&#160;&#160;&#160;0x000C</td></tr>
<tr class="memdesc:ga54fd2c392399221077c67866a395e587"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass.  <a href="#ga54fd2c392399221077c67866a395e587">More...</a><br/></td></tr>
<tr class="separator:ga54fd2c392399221077c67866a395e587"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756">ARM_PMU_BR_IMMED_RETIRED</a>&#160;&#160;&#160;0x000D</td></tr>
<tr class="memdesc:ga22bfb189fff7c1ea9f81097a543ed756"><td class="mdescLeft">&#160;</td><td class="mdescRight">Immediate branch architecturally executed.  <a href="#ga22bfb189fff7c1ea9f81097a543ed756">More...</a><br/></td></tr>
<tr class="separator:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5">ARM_PMU_BR_RETURN_RETIRED</a>&#160;&#160;&#160;0x000E</td></tr>
<tr class="memdesc:gab717347b1c3601cffb9c99b43b2a45c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function return instruction architecturally executed and the condition code check pass.  <a href="#gab717347b1c3601cffb9c99b43b2a45c5">More...</a><br/></td></tr>
<tr class="separator:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45d5ea86fdc015f4fc100462150c92da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga45d5ea86fdc015f4fc100462150c92da">ARM_PMU_UNALIGNED_LDST_RETIRED</a>&#160;&#160;&#160;0x000F</td></tr>
<tr class="memdesc:ga45d5ea86fdc015f4fc100462150c92da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass.  <a href="#ga45d5ea86fdc015f4fc100462150c92da">More...</a><br/></td></tr>
<tr class="separator:ga45d5ea86fdc015f4fc100462150c92da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfa921c85a61f0a21c9bee289e63c102"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102">ARM_PMU_BR_MIS_PRED</a>&#160;&#160;&#160;0x0010</td></tr>
<tr class="memdesc:gabfa921c85a61f0a21c9bee289e63c102"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mispredicted or not predicted branch speculatively executed.  <a href="#gabfa921c85a61f0a21c9bee289e63c102">More...</a><br/></td></tr>
<tr class="separator:gabfa921c85a61f0a21c9bee289e63c102"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga550d524d435a653b2f46acc1380a5ace"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace">ARM_PMU_CPU_CYCLES</a>&#160;&#160;&#160;0x0011</td></tr>
<tr class="memdesc:ga550d524d435a653b2f46acc1380a5ace"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cycle.  <a href="#ga550d524d435a653b2f46acc1380a5ace">More...</a><br/></td></tr>
<tr class="separator:ga550d524d435a653b2f46acc1380a5ace"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga60ccf42eae576e2fde3b9e17a8defeaa">ARM_PMU_BR_PRED</a>&#160;&#160;&#160;0x0012</td></tr>
<tr class="memdesc:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Predictable branch speculatively executed.  <a href="#ga60ccf42eae576e2fde3b9e17a8defeaa">More...</a><br/></td></tr>
<tr class="separator:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3852c2b3d59af106b9db7ea2c20c367">ARM_PMU_MEM_ACCESS</a>&#160;&#160;&#160;0x0013</td></tr>
<tr class="memdesc:gab3852c2b3d59af106b9db7ea2c20c367"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data memory access.  <a href="#gab3852c2b3d59af106b9db7ea2c20c367">More...</a><br/></td></tr>
<tr class="separator:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8e89b2b098e6bec5916517346925ce2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf8e89b2b098e6bec5916517346925ce2">ARM_PMU_L1I_CACHE</a>&#160;&#160;&#160;0x0014</td></tr>
<tr class="memdesc:gaf8e89b2b098e6bec5916517346925ce2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 instruction cache access.  <a href="#gaf8e89b2b098e6bec5916517346925ce2">More...</a><br/></td></tr>
<tr class="separator:gaf8e89b2b098e6bec5916517346925ce2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0">ARM_PMU_L1D_CACHE_WB</a>&#160;&#160;&#160;0x0015</td></tr>
<tr class="memdesc:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache write-back.  <a href="#ga27d1b8b2c37ae0ae41781880ed3893d0">More...</a><br/></td></tr>
<tr class="separator:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb1e1f86d091ccb735858769c700e289"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafb1e1f86d091ccb735858769c700e289">ARM_PMU_L2D_CACHE</a>&#160;&#160;&#160;0x0016</td></tr>
<tr class="memdesc:gafb1e1f86d091ccb735858769c700e289"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache access.  <a href="#gafb1e1f86d091ccb735858769c700e289">More...</a><br/></td></tr>
<tr class="separator:gafb1e1f86d091ccb735858769c700e289"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb414c1b0375022abc2502ab503a3284"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaeb414c1b0375022abc2502ab503a3284">ARM_PMU_L2D_CACHE_REFILL</a>&#160;&#160;&#160;0x0017</td></tr>
<tr class="memdesc:gaeb414c1b0375022abc2502ab503a3284"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache refill.  <a href="#gaeb414c1b0375022abc2502ab503a3284">More...</a><br/></td></tr>
<tr class="separator:gaeb414c1b0375022abc2502ab503a3284"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">ARM_PMU_L2D_CACHE_WB</a>&#160;&#160;&#160;0x0018</td></tr>
<tr class="memdesc:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache write-back.  <a href="#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">More...</a><br/></td></tr>
<tr class="separator:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa681d3db56b42775093869b8fdf1abb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9">ARM_PMU_BUS_ACCESS</a>&#160;&#160;&#160;0x0019</td></tr>
<tr class="memdesc:gaa681d3db56b42775093869b8fdf1abb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus access.  <a href="#gaa681d3db56b42775093869b8fdf1abb9">More...</a><br/></td></tr>
<tr class="separator:gaa681d3db56b42775093869b8fdf1abb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">ARM_PMU_MEMORY_ERROR</a>&#160;&#160;&#160;0x001A</td></tr>
<tr class="memdesc:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local memory error.  <a href="#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">More...</a><br/></td></tr>
<tr class="separator:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7">ARM_PMU_INST_SPEC</a>&#160;&#160;&#160;0x001B</td></tr>
<tr class="memdesc:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction speculatively executed.  <a href="#gaf7bad54617ace5c2fb48bc2e8aebf9c7">More...</a><br/></td></tr>
<tr class="separator:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4c955416707f44f066ffd2560b9ae4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c">ARM_PMU_BUS_CYCLES</a>&#160;&#160;&#160;0x001D</td></tr>
<tr class="memdesc:gae4c955416707f44f066ffd2560b9ae4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus cycles.  <a href="#gae4c955416707f44f066ffd2560b9ae4c">More...</a><br/></td></tr>
<tr class="separator:gae4c955416707f44f066ffd2560b9ae4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0">ARM_PMU_CHAIN</a>&#160;&#160;&#160;0x001E</td></tr>
<tr class="memdesc:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="mdescLeft">&#160;</td><td class="mdescRight">For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE.  <a href="#gaca14907c5a1e1f9915159bc4cf323cf0">More...</a><br/></td></tr>
<tr class="separator:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab55334c8510cb30c4c750913f6eb6279"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279">ARM_PMU_L1D_CACHE_ALLOCATE</a>&#160;&#160;&#160;0x001F</td></tr>
<tr class="memdesc:gab55334c8510cb30c4c750913f6eb6279"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache allocation without refill.  <a href="#gab55334c8510cb30c4c750913f6eb6279">More...</a><br/></td></tr>
<tr class="separator:gab55334c8510cb30c4c750913f6eb6279"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad08dcded491bf257d223e4171af41cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaad08dcded491bf257d223e4171af41cc">ARM_PMU_L2D_CACHE_ALLOCATE</a>&#160;&#160;&#160;0x0020</td></tr>
<tr class="memdesc:gaad08dcded491bf257d223e4171af41cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache allocation without refill.  <a href="#gaad08dcded491bf257d223e4171af41cc">More...</a><br/></td></tr>
<tr class="separator:gaad08dcded491bf257d223e4171af41cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3b505a8bcc2b2885626d2f2cd542b73">ARM_PMU_BR_RETIRED</a>&#160;&#160;&#160;0x0021</td></tr>
<tr class="memdesc:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Branch instruction architecturally executed.  <a href="#gab3b505a8bcc2b2885626d2f2cd542b73">More...</a><br/></td></tr>
<tr class="separator:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae12baa616c5f0cdd081231fcf8cdad68">ARM_PMU_BR_MIS_PRED_RETIRED</a>&#160;&#160;&#160;0x0022</td></tr>
<tr class="memdesc:gae12baa616c5f0cdd081231fcf8cdad68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mispredicted branch instruction architecturally executed.  <a href="#gae12baa616c5f0cdd081231fcf8cdad68">More...</a><br/></td></tr>
<tr class="separator:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b068593baa831348664dfa7d44f5483"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b068593baa831348664dfa7d44f5483">ARM_PMU_STALL_FRONTEND</a>&#160;&#160;&#160;0x0023</td></tr>
<tr class="memdesc:ga5b068593baa831348664dfa7d44f5483"><td class="mdescLeft">&#160;</td><td class="mdescRight">No operation issued because of the frontend.  <a href="#ga5b068593baa831348664dfa7d44f5483">More...</a><br/></td></tr>
<tr class="separator:ga5b068593baa831348664dfa7d44f5483"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8737bee352820bd7d1bc8e5e4260143c">ARM_PMU_STALL_BACKEND</a>&#160;&#160;&#160;0x0024</td></tr>
<tr class="memdesc:ga8737bee352820bd7d1bc8e5e4260143c"><td class="mdescLeft">&#160;</td><td class="mdescRight">No operation issued because of the backend.  <a href="#ga8737bee352820bd7d1bc8e5e4260143c">More...</a><br/></td></tr>
<tr class="separator:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3406498b2c17ca080ebd68cc40d9630e">ARM_PMU_L2I_CACHE</a>&#160;&#160;&#160;0x0027</td></tr>
<tr class="memdesc:ga3406498b2c17ca080ebd68cc40d9630e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 instruction cache access.  <a href="#ga3406498b2c17ca080ebd68cc40d9630e">More...</a><br/></td></tr>
<tr class="separator:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa18cee03802b46076e9ab66fd0a7c61d">ARM_PMU_L2I_CACHE_REFILL</a>&#160;&#160;&#160;0x0028</td></tr>
<tr class="memdesc:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 instruction cache refill.  <a href="#gaa18cee03802b46076e9ab66fd0a7c61d">More...</a><br/></td></tr>
<tr class="separator:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">ARM_PMU_L3D_CACHE_ALLOCATE</a>&#160;&#160;&#160;0x0029</td></tr>
<tr class="memdesc:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache allocation without refill.  <a href="#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">More...</a><br/></td></tr>
<tr class="separator:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe99db0693125100272247c147fb3b02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafe99db0693125100272247c147fb3b02">ARM_PMU_L3D_CACHE_REFILL</a>&#160;&#160;&#160;0x002A</td></tr>
<tr class="memdesc:gafe99db0693125100272247c147fb3b02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache refill.  <a href="#gafe99db0693125100272247c147fb3b02">More...</a><br/></td></tr>
<tr class="separator:gafe99db0693125100272247c147fb3b02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e96b5a6fb13c657e78da342a02db200"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4e96b5a6fb13c657e78da342a02db200">ARM_PMU_L3D_CACHE</a>&#160;&#160;&#160;0x002B</td></tr>
<tr class="memdesc:ga4e96b5a6fb13c657e78da342a02db200"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache access.  <a href="#ga4e96b5a6fb13c657e78da342a02db200">More...</a><br/></td></tr>
<tr class="separator:ga4e96b5a6fb13c657e78da342a02db200"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab823f95f7ac8196a208d12381b1b2a11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab823f95f7ac8196a208d12381b1b2a11">ARM_PMU_L3D_CACHE_WB</a>&#160;&#160;&#160;0x002C</td></tr>
<tr class="memdesc:gab823f95f7ac8196a208d12381b1b2a11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache write-back.  <a href="#gab823f95f7ac8196a208d12381b1b2a11">More...</a><br/></td></tr>
<tr class="separator:gab823f95f7ac8196a208d12381b1b2a11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga902562d8161fffd45726dc4cc8727545"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga902562d8161fffd45726dc4cc8727545">ARM_PMU_LL_CACHE_RD</a>&#160;&#160;&#160;0x0036</td></tr>
<tr class="memdesc:ga902562d8161fffd45726dc4cc8727545"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last level data cache read.  <a href="#ga902562d8161fffd45726dc4cc8727545">More...</a><br/></td></tr>
<tr class="separator:ga902562d8161fffd45726dc4cc8727545"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6979efa69af7d0e62cc3e2f88b0155b8">ARM_PMU_LL_CACHE_MISS_RD</a>&#160;&#160;&#160;0x0037</td></tr>
<tr class="memdesc:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last level data cache read miss.  <a href="#ga6979efa69af7d0e62cc3e2f88b0155b8">More...</a><br/></td></tr>
<tr class="separator:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">ARM_PMU_L1D_CACHE_MISS_RD</a>&#160;&#160;&#160;0x0039</td></tr>
<tr class="memdesc:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache read miss.  <a href="#ga4687d5d7efc6f49db2db9acc25b590f6">More...</a><br/></td></tr>
<tr class="separator:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2fe9d3ea67ce833bd6323e4ce1a4e894">ARM_PMU_OP_COMPLETE</a>&#160;&#160;&#160;0x003A</td></tr>
<tr class="memdesc:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="mdescLeft">&#160;</td><td class="mdescRight">Operation retired.  <a href="#ga2fe9d3ea67ce833bd6323e4ce1a4e894">More...</a><br/></td></tr>
<tr class="separator:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c59149e9b1754987b44b62092bc9f09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6c59149e9b1754987b44b62092bc9f09">ARM_PMU_OP_SPEC</a>&#160;&#160;&#160;0x003B</td></tr>
<tr class="memdesc:ga6c59149e9b1754987b44b62092bc9f09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Operation speculatively executed.  <a href="#ga6c59149e9b1754987b44b62092bc9f09">More...</a><br/></td></tr>
<tr class="separator:ga6c59149e9b1754987b44b62092bc9f09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8bf75efa06a125ee2dfa9a130e7ba9a8">ARM_PMU_STALL</a>&#160;&#160;&#160;0x003C</td></tr>
<tr class="memdesc:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution.  <a href="#ga8bf75efa06a125ee2dfa9a130e7ba9a8">More...</a><br/></td></tr>
<tr class="separator:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9700ec74727a9fe3cd4cd40736628a23">ARM_PMU_STALL_OP_BACKEND</a>&#160;&#160;&#160;0x003D</td></tr>
<tr class="memdesc:ga9700ec74727a9fe3cd4cd40736628a23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline backend.  <a href="#ga9700ec74727a9fe3cd4cd40736628a23">More...</a><br/></td></tr>
<tr class="separator:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga69cfd3558cf6c6f3bb621ee75430427c">ARM_PMU_STALL_OP_FRONTEND</a>&#160;&#160;&#160;0x003E</td></tr>
<tr class="memdesc:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline frontend.  <a href="#ga69cfd3558cf6c6f3bb621ee75430427c">More...</a><br/></td></tr>
<tr class="separator:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga197b491f691110fb52aef4291782b6ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga197b491f691110fb52aef4291782b6ab">ARM_PMU_STALL_OP</a>&#160;&#160;&#160;0x003F</td></tr>
<tr class="memdesc:ga197b491f691110fb52aef4291782b6ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction or operation slots not occupied each cycle.  <a href="#ga197b491f691110fb52aef4291782b6ab">More...</a><br/></td></tr>
<tr class="separator:ga197b491f691110fb52aef4291782b6ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77">ARM_PMU_L1D_CACHE_RD</a>&#160;&#160;&#160;0x0040</td></tr>
<tr class="memdesc:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache read.  <a href="#gaf4236dfbcb4550d3cc98caee837e8e77">More...</a><br/></td></tr>
<tr class="separator:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga345461506c990125b1f2cbc62e3be22f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga345461506c990125b1f2cbc62e3be22f">ARM_PMU_LE_RETIRED</a>&#160;&#160;&#160;0x0100</td></tr>
<tr class="memdesc:ga345461506c990125b1f2cbc62e3be22f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop end instruction executed.  <a href="#ga345461506c990125b1f2cbc62e3be22f">More...</a><br/></td></tr>
<tr class="separator:ga345461506c990125b1f2cbc62e3be22f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a1d9f84bda091e96843665ff3913b50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6a1d9f84bda091e96843665ff3913b50">ARM_PMU_LE_SPEC</a>&#160;&#160;&#160;0x0101</td></tr>
<tr class="memdesc:ga6a1d9f84bda091e96843665ff3913b50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop end instruction speculatively executed.  <a href="#ga6a1d9f84bda091e96843665ff3913b50">More...</a><br/></td></tr>
<tr class="separator:ga6a1d9f84bda091e96843665ff3913b50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8570f46393e3e44bb118591d33723f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab8570f46393e3e44bb118591d33723f4">ARM_PMU_BF_RETIRED</a>&#160;&#160;&#160;0x0104</td></tr>
<tr class="memdesc:gab8570f46393e3e44bb118591d33723f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Branch future instruction architecturally executed and condition code check pass.  <a href="#gab8570f46393e3e44bb118591d33723f4">More...</a><br/></td></tr>
<tr class="separator:gab8570f46393e3e44bb118591d33723f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6b1e4823d8b45678a29a5f54b859d4e3">ARM_PMU_BF_SPEC</a>&#160;&#160;&#160;0x0105</td></tr>
<tr class="memdesc:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Branch future instruction speculatively executed and condition code check pass.  <a href="#ga6b1e4823d8b45678a29a5f54b859d4e3">More...</a><br/></td></tr>
<tr class="separator:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8b5641a3cb0e922a2b4e16ec14052861">ARM_PMU_LE_CANCEL</a>&#160;&#160;&#160;0x0108</td></tr>
<tr class="memdesc:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop end instruction not taken.  <a href="#ga8b5641a3cb0e922a2b4e16ec14052861">More...</a><br/></td></tr>
<tr class="separator:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf2e0a38b7c0d63d1194f08478781a3f0">ARM_PMU_BF_CANCEL</a>&#160;&#160;&#160;0x0109</td></tr>
<tr class="memdesc:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Branch future instruction not taken.  <a href="#gaf2e0a38b7c0d63d1194f08478781a3f0">More...</a><br/></td></tr>
<tr class="separator:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad3ba2effbe303ca3fafdbc022fe206c1">ARM_PMU_SE_CALL_S</a>&#160;&#160;&#160;0x0114</td></tr>
<tr class="memdesc:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Call to secure function, resulting in Security state change.  <a href="#gad3ba2effbe303ca3fafdbc022fe206c1">More...</a><br/></td></tr>
<tr class="separator:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaaae2c32a8ecd36b59ac98cf8e23b3cab">ARM_PMU_SE_CALL_NS</a>&#160;&#160;&#160;0x0115</td></tr>
<tr class="memdesc:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Call to non-secure function, resulting in Security state change.  <a href="#gaaae2c32a8ecd36b59ac98cf8e23b3cab">More...</a><br/></td></tr>
<tr class="separator:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga18d640aa04b97c7d287e8745f6f2b23d">ARM_PMU_DWT_CMPMATCH0</a>&#160;&#160;&#160;0x0118</td></tr>
<tr class="memdesc:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DWT comparator 0 match.  <a href="#ga18d640aa04b97c7d287e8745f6f2b23d">More...</a><br/></td></tr>
<tr class="separator:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">ARM_PMU_DWT_CMPMATCH1</a>&#160;&#160;&#160;0x0119</td></tr>
<tr class="memdesc:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">DWT comparator 1 match.  <a href="#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">More...</a><br/></td></tr>
<tr class="separator:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga58a4815dba8886088b9cac7b934a332d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga58a4815dba8886088b9cac7b934a332d">ARM_PMU_DWT_CMPMATCH2</a>&#160;&#160;&#160;0x011A</td></tr>
<tr class="memdesc:ga58a4815dba8886088b9cac7b934a332d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DWT comparator 2 match.  <a href="#ga58a4815dba8886088b9cac7b934a332d">More...</a><br/></td></tr>
<tr class="separator:ga58a4815dba8886088b9cac7b934a332d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga594337c6f3c88d8317203a8cd6f9814a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga594337c6f3c88d8317203a8cd6f9814a">ARM_PMU_DWT_CMPMATCH3</a>&#160;&#160;&#160;0x011B</td></tr>
<tr class="memdesc:ga594337c6f3c88d8317203a8cd6f9814a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DWT comparator 3 match.  <a href="#ga594337c6f3c88d8317203a8cd6f9814a">More...</a><br/></td></tr>
<tr class="separator:ga594337c6f3c88d8317203a8cd6f9814a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c1006bed2fb82b0749386261b397727"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3c1006bed2fb82b0749386261b397727">ARM_PMU_MVE_INST_RETIRED</a>&#160;&#160;&#160;0x0200</td></tr>
<tr class="memdesc:ga3c1006bed2fb82b0749386261b397727"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE instruction architecturally executed.  <a href="#ga3c1006bed2fb82b0749386261b397727">More...</a><br/></td></tr>
<tr class="separator:ga3c1006bed2fb82b0749386261b397727"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e276b6872345eb3b043626a11f235c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1e276b6872345eb3b043626a11f235c6">ARM_PMU_MVE_INST_SPEC</a>&#160;&#160;&#160;0x0201</td></tr>
<tr class="memdesc:ga1e276b6872345eb3b043626a11f235c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE instruction speculatively executed.  <a href="#ga1e276b6872345eb3b043626a11f235c6">More...</a><br/></td></tr>
<tr class="separator:ga1e276b6872345eb3b043626a11f235c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga268b0bcbd30e8a928bd0f331fdf53ccf">ARM_PMU_MVE_FP_RETIRED</a>&#160;&#160;&#160;0x0204</td></tr>
<tr class="memdesc:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE floating-point instruction architecturally executed.  <a href="#ga268b0bcbd30e8a928bd0f331fdf53ccf">More...</a><br/></td></tr>
<tr class="separator:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadf9cfd45b59acfc314ebc814a1bcdccd">ARM_PMU_MVE_FP_SPEC</a>&#160;&#160;&#160;0x0205</td></tr>
<tr class="memdesc:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE floating-point instruction speculatively executed.  <a href="#gadf9cfd45b59acfc314ebc814a1bcdccd">More...</a><br/></td></tr>
<tr class="separator:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa4c408a006a04e95ade26922669b6695"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa4c408a006a04e95ade26922669b6695">ARM_PMU_MVE_FP_HP_RETIRED</a>&#160;&#160;&#160;0x0208</td></tr>
<tr class="memdesc:gaa4c408a006a04e95ade26922669b6695"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE half-precision floating-point instruction architecturally executed.  <a href="#gaa4c408a006a04e95ade26922669b6695">More...</a><br/></td></tr>
<tr class="separator:gaa4c408a006a04e95ade26922669b6695"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf01d187b0cbf418d1fac55dd0ddd0827">ARM_PMU_MVE_FP_HP_SPEC</a>&#160;&#160;&#160;0x0209</td></tr>
<tr class="memdesc:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE half-precision floating-point instruction speculatively executed.  <a href="#gaf01d187b0cbf418d1fac55dd0ddd0827">More...</a><br/></td></tr>
<tr class="separator:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab21171c50ebd1f304b11260edd015f52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab21171c50ebd1f304b11260edd015f52">ARM_PMU_MVE_FP_SP_RETIRED</a>&#160;&#160;&#160;0x020C</td></tr>
<tr class="memdesc:gab21171c50ebd1f304b11260edd015f52"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE single-precision floating-point instruction architecturally executed.  <a href="#gab21171c50ebd1f304b11260edd015f52">More...</a><br/></td></tr>
<tr class="separator:gab21171c50ebd1f304b11260edd015f52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae69e310892661af852ca2d4ec947d18a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae69e310892661af852ca2d4ec947d18a">ARM_PMU_MVE_FP_SP_SPEC</a>&#160;&#160;&#160;0x020D</td></tr>
<tr class="memdesc:gae69e310892661af852ca2d4ec947d18a"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE single-precision floating-point instruction speculatively executed.  <a href="#gae69e310892661af852ca2d4ec947d18a">More...</a><br/></td></tr>
<tr class="separator:gae69e310892661af852ca2d4ec947d18a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac2dc7d92627b3caa391725a3f080288c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac2dc7d92627b3caa391725a3f080288c">ARM_PMU_MVE_FP_MAC_RETIRED</a>&#160;&#160;&#160;0x0214</td></tr>
<tr class="memdesc:gac2dc7d92627b3caa391725a3f080288c"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE floating-point multiply or multiply-accumulate instruction architecturally executed.  <a href="#gac2dc7d92627b3caa391725a3f080288c">More...</a><br/></td></tr>
<tr class="separator:gac2dc7d92627b3caa391725a3f080288c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5302b3278a862c9264171955328a59a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf5302b3278a862c9264171955328a59a">ARM_PMU_MVE_FP_MAC_SPEC</a>&#160;&#160;&#160;0x0215</td></tr>
<tr class="memdesc:gaf5302b3278a862c9264171955328a59a"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE floating-point multiply or multiply-accumulate instruction speculatively executed.  <a href="#gaf5302b3278a862c9264171955328a59a">More...</a><br/></td></tr>
<tr class="separator:gaf5302b3278a862c9264171955328a59a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5e3afafa91ebaeac0469a19ebb54719c">ARM_PMU_MVE_INT_RETIRED</a>&#160;&#160;&#160;0x0224</td></tr>
<tr class="memdesc:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE integer instruction architecturally executed.  <a href="#ga5e3afafa91ebaeac0469a19ebb54719c">More...</a><br/></td></tr>
<tr class="separator:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16ed0bb1bb4718da93c41238da652d33"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga16ed0bb1bb4718da93c41238da652d33">ARM_PMU_MVE_INT_SPEC</a>&#160;&#160;&#160;0x0225</td></tr>
<tr class="memdesc:ga16ed0bb1bb4718da93c41238da652d33"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE integer instruction speculatively executed.  <a href="#ga16ed0bb1bb4718da93c41238da652d33">More...</a><br/></td></tr>
<tr class="separator:ga16ed0bb1bb4718da93c41238da652d33"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9248c93a3f19fddc93d3804a06f7238a">ARM_PMU_MVE_INT_MAC_RETIRED</a>&#160;&#160;&#160;0x0228</td></tr>
<tr class="memdesc:ga9248c93a3f19fddc93d3804a06f7238a"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE multiply or multiply-accumulate instruction architecturally executed.  <a href="#ga9248c93a3f19fddc93d3804a06f7238a">More...</a><br/></td></tr>
<tr class="separator:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7036f00faa9183ae450a3e4d9d6f2bbf">ARM_PMU_MVE_INT_MAC_SPEC</a>&#160;&#160;&#160;0x0229</td></tr>
<tr class="memdesc:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE multiply or multiply-accumulate instruction speculatively executed.  <a href="#ga7036f00faa9183ae450a3e4d9d6f2bbf">More...</a><br/></td></tr>
<tr class="separator:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7d7d465a6c64400c49f93b6c8152296f">ARM_PMU_MVE_LDST_RETIRED</a>&#160;&#160;&#160;0x0238</td></tr>
<tr class="memdesc:ga7d7d465a6c64400c49f93b6c8152296f"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE load or store instruction architecturally executed.  <a href="#ga7d7d465a6c64400c49f93b6c8152296f">More...</a><br/></td></tr>
<tr class="separator:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa98a18c06bd13daf2df6f89219ec68d5">ARM_PMU_MVE_LDST_SPEC</a>&#160;&#160;&#160;0x0239</td></tr>
<tr class="memdesc:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE load or store instruction speculatively executed.  <a href="#gaa98a18c06bd13daf2df6f89219ec68d5">More...</a><br/></td></tr>
<tr class="separator:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa3379a51350a2fda8d8ab6d7795baa7a">ARM_PMU_MVE_LD_RETIRED</a>&#160;&#160;&#160;0x023C</td></tr>
<tr class="memdesc:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE load instruction architecturally executed.  <a href="#gaa3379a51350a2fda8d8ab6d7795baa7a">More...</a><br/></td></tr>
<tr class="separator:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga78a6f89ab30ed01f7d8388eda697b4f8">ARM_PMU_MVE_LD_SPEC</a>&#160;&#160;&#160;0x023D</td></tr>
<tr class="memdesc:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE load instruction speculatively executed.  <a href="#ga78a6f89ab30ed01f7d8388eda697b4f8">More...</a><br/></td></tr>
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<tr class="memitem:gad8d0079977fa97de4ee263703f1b2908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad8d0079977fa97de4ee263703f1b2908">ARM_PMU_MVE_ST_RETIRED</a>&#160;&#160;&#160;0x0240</td></tr>
<tr class="memdesc:gad8d0079977fa97de4ee263703f1b2908"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE store instruction architecturally executed.  <a href="#gad8d0079977fa97de4ee263703f1b2908">More...</a><br/></td></tr>
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<tr class="memitem:gabd3984d299b5416aac8d630722680c55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabd3984d299b5416aac8d630722680c55">ARM_PMU_MVE_ST_SPEC</a>&#160;&#160;&#160;0x0241</td></tr>
<tr class="memdesc:gabd3984d299b5416aac8d630722680c55"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE store instruction speculatively executed.  <a href="#gabd3984d299b5416aac8d630722680c55">More...</a><br/></td></tr>
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<tr class="memitem:ga8acf6a66c63798b76608caf52c96658d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8acf6a66c63798b76608caf52c96658d">ARM_PMU_MVE_LDST_CONTIG_RETIRED</a>&#160;&#160;&#160;0x0244</td></tr>
<tr class="memdesc:ga8acf6a66c63798b76608caf52c96658d"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE contiguous load or store instruction architecturally executed.  <a href="#ga8acf6a66c63798b76608caf52c96658d">More...</a><br/></td></tr>
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<tr class="memitem:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5a83ef6a52739e1d223be503bbdaaab6">ARM_PMU_MVE_LDST_CONTIG_SPEC</a>&#160;&#160;&#160;0x0245</td></tr>
<tr class="memdesc:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE contiguous load or store instruction speculatively executed.  <a href="#ga5a83ef6a52739e1d223be503bbdaaab6">More...</a><br/></td></tr>
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<tr class="memitem:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8732a737f2b7adc43e3d1da7b3da92e6">ARM_PMU_MVE_LD_CONTIG_RETIRED</a>&#160;&#160;&#160;0x0248</td></tr>
<tr class="memdesc:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE contiguous load instruction architecturally executed.  <a href="#ga8732a737f2b7adc43e3d1da7b3da92e6">More...</a><br/></td></tr>
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<tr class="memitem:ga8e58fe07254256fa3bf3d42fa2062141"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8e58fe07254256fa3bf3d42fa2062141">ARM_PMU_MVE_LD_CONTIG_SPEC</a>&#160;&#160;&#160;0x0249</td></tr>
<tr class="memdesc:ga8e58fe07254256fa3bf3d42fa2062141"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE contiguous load instruction speculatively executed.  <a href="#ga8e58fe07254256fa3bf3d42fa2062141">More...</a><br/></td></tr>
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<tr class="memitem:gacb3c0b922eae9aac321df97ec889e0ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gacb3c0b922eae9aac321df97ec889e0ed">ARM_PMU_MVE_ST_CONTIG_RETIRED</a>&#160;&#160;&#160;0x024C</td></tr>
<tr class="memdesc:gacb3c0b922eae9aac321df97ec889e0ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE contiguous store instruction architecturally executed.  <a href="#gacb3c0b922eae9aac321df97ec889e0ed">More...</a><br/></td></tr>
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<tr class="memitem:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga02cd64b9444e4babc7b69e8571d39bdd">ARM_PMU_MVE_ST_CONTIG_SPEC</a>&#160;&#160;&#160;0x024D</td></tr>
<tr class="memdesc:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE contiguous store instruction speculatively executed.  <a href="#ga02cd64b9444e4babc7b69e8571d39bdd">More...</a><br/></td></tr>
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<tr class="memitem:ga7065b7f0aea461858b72912d22c329f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7065b7f0aea461858b72912d22c329f2">ARM_PMU_MVE_LDST_NONCONTIG_RETIRED</a>&#160;&#160;&#160;0x0250</td></tr>
<tr class="memdesc:ga7065b7f0aea461858b72912d22c329f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE non-contiguous load or store instruction architecturally executed.  <a href="#ga7065b7f0aea461858b72912d22c329f2">More...</a><br/></td></tr>
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<tr class="memitem:ga193605eb52709741d91a64e3ad1a5894"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga193605eb52709741d91a64e3ad1a5894">ARM_PMU_MVE_LDST_NONCONTIG_SPEC</a>&#160;&#160;&#160;0x0251</td></tr>
<tr class="memdesc:ga193605eb52709741d91a64e3ad1a5894"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE non-contiguous load or store instruction speculatively executed.  <a href="#ga193605eb52709741d91a64e3ad1a5894">More...</a><br/></td></tr>
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<tr class="memitem:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">ARM_PMU_MVE_LD_NONCONTIG_RETIRED</a>&#160;&#160;&#160;0x0254</td></tr>
<tr class="memdesc:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE non-contiguous load instruction architecturally executed.  <a href="#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">More...</a><br/></td></tr>
<tr class="separator:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadbcb82b7924b7bbee5c0d42a3de38572">ARM_PMU_MVE_LD_NONCONTIG_SPEC</a>&#160;&#160;&#160;0x0255</td></tr>
<tr class="memdesc:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE non-contiguous load instruction speculatively executed.  <a href="#gadbcb82b7924b7bbee5c0d42a3de38572">More...</a><br/></td></tr>
<tr class="separator:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8271f415ecc7573b57e82a24aec86ef1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8271f415ecc7573b57e82a24aec86ef1">ARM_PMU_MVE_ST_NONCONTIG_RETIRED</a>&#160;&#160;&#160;0x0258</td></tr>
<tr class="memdesc:ga8271f415ecc7573b57e82a24aec86ef1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE non-contiguous store instruction architecturally executed.  <a href="#ga8271f415ecc7573b57e82a24aec86ef1">More...</a><br/></td></tr>
<tr class="separator:ga8271f415ecc7573b57e82a24aec86ef1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga059327c80f396918a9f8192bcd0fa4a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga059327c80f396918a9f8192bcd0fa4a8">ARM_PMU_MVE_ST_NONCONTIG_SPEC</a>&#160;&#160;&#160;0x0259</td></tr>
<tr class="memdesc:ga059327c80f396918a9f8192bcd0fa4a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE non-contiguous store instruction speculatively executed.  <a href="#ga059327c80f396918a9f8192bcd0fa4a8">More...</a><br/></td></tr>
<tr class="separator:ga059327c80f396918a9f8192bcd0fa4a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d669378441408fc21aa551e483866cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7d669378441408fc21aa551e483866cb">ARM_PMU_MVE_LDST_MULTI_RETIRED</a>&#160;&#160;&#160;0x025C</td></tr>
<tr class="memdesc:ga7d669378441408fc21aa551e483866cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE memory instruction targeting multiple registers architecturally executed.  <a href="#ga7d669378441408fc21aa551e483866cb">More...</a><br/></td></tr>
<tr class="separator:ga7d669378441408fc21aa551e483866cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7ea46cde08cb0cc4a46ef23835fb5aac">ARM_PMU_MVE_LDST_MULTI_SPEC</a>&#160;&#160;&#160;0x025D</td></tr>
<tr class="memdesc:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE memory instruction targeting multiple registers speculatively executed.  <a href="#ga7ea46cde08cb0cc4a46ef23835fb5aac">More...</a><br/></td></tr>
<tr class="separator:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga50fb13c874b3f5e2b9ed9c320a36452c">ARM_PMU_MVE_LD_MULTI_RETIRED</a>&#160;&#160;&#160;0x0260</td></tr>
<tr class="memdesc:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE memory load instruction targeting multiple registers architecturally executed.  <a href="#ga50fb13c874b3f5e2b9ed9c320a36452c">More...</a><br/></td></tr>
<tr class="separator:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf2d4e3d1f06d97899de7fa791477d62b">ARM_PMU_MVE_LD_MULTI_SPEC</a>&#160;&#160;&#160;0x0261</td></tr>
<tr class="memdesc:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE memory load instruction targeting multiple registers speculatively executed.  <a href="#gaf2d4e3d1f06d97899de7fa791477d62b">More...</a><br/></td></tr>
<tr class="separator:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga76057cbda353b4ad6fbc3b6a63c193a5">ARM_PMU_MVE_ST_MULTI_RETIRED</a>&#160;&#160;&#160;0x0261</td></tr>
<tr class="memdesc:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE memory store instruction targeting multiple registers architecturally executed.  <a href="#ga76057cbda353b4ad6fbc3b6a63c193a5">More...</a><br/></td></tr>
<tr class="separator:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6a14402c79dba8fa765e8663dd0734d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf6a14402c79dba8fa765e8663dd0734d">ARM_PMU_MVE_ST_MULTI_SPEC</a>&#160;&#160;&#160;0x0265</td></tr>
<tr class="memdesc:gaf6a14402c79dba8fa765e8663dd0734d"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE memory store instruction targeting multiple registers speculatively executed.  <a href="#gaf6a14402c79dba8fa765e8663dd0734d">More...</a><br/></td></tr>
<tr class="separator:gaf6a14402c79dba8fa765e8663dd0734d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf358a9ed5c83a10cb695d9b19b1b3bc1">ARM_PMU_MVE_LDST_UNALIGNED_RETIRED</a>&#160;&#160;&#160;0x028C</td></tr>
<tr class="memdesc:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned memory load or store instruction architecturally executed.  <a href="#gaf358a9ed5c83a10cb695d9b19b1b3bc1">More...</a><br/></td></tr>
<tr class="separator:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2264786bed578c89109859b55909c76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab2264786bed578c89109859b55909c76">ARM_PMU_MVE_LDST_UNALIGNED_SPEC</a>&#160;&#160;&#160;0x028D</td></tr>
<tr class="memdesc:gab2264786bed578c89109859b55909c76"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned memory load or store instruction speculatively executed.  <a href="#gab2264786bed578c89109859b55909c76">More...</a><br/></td></tr>
<tr class="separator:gab2264786bed578c89109859b55909c76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga26ed05deaa7b993904300069f0ecfac4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga26ed05deaa7b993904300069f0ecfac4">ARM_PMU_MVE_LD_UNALIGNED_RETIRED</a>&#160;&#160;&#160;0x0290</td></tr>
<tr class="memdesc:ga26ed05deaa7b993904300069f0ecfac4"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned load instruction architecturally executed.  <a href="#ga26ed05deaa7b993904300069f0ecfac4">More...</a><br/></td></tr>
<tr class="separator:ga26ed05deaa7b993904300069f0ecfac4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadc3bd0f32e0a08bba2d533479a59bd6e">ARM_PMU_MVE_LD_UNALIGNED_SPEC</a>&#160;&#160;&#160;0x0291</td></tr>
<tr class="memdesc:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned load instruction speculatively executed.  <a href="#gadc3bd0f32e0a08bba2d533479a59bd6e">More...</a><br/></td></tr>
<tr class="separator:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga391afd8cb92cc65161b13ee3a3256d40">ARM_PMU_MVE_ST_UNALIGNED_RETIRED</a>&#160;&#160;&#160;0x0294</td></tr>
<tr class="memdesc:ga391afd8cb92cc65161b13ee3a3256d40"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned store instruction architecturally executed.  <a href="#ga391afd8cb92cc65161b13ee3a3256d40">More...</a><br/></td></tr>
<tr class="separator:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21bf105499df85196b4137cb075a6fbe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga21bf105499df85196b4137cb075a6fbe">ARM_PMU_MVE_ST_UNALIGNED_SPEC</a>&#160;&#160;&#160;0x0295</td></tr>
<tr class="memdesc:ga21bf105499df85196b4137cb075a6fbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned store instruction speculatively executed.  <a href="#ga21bf105499df85196b4137cb075a6fbe">More...</a><br/></td></tr>
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<tr class="memitem:ga627920bebd935709655687d844848934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga627920bebd935709655687d844848934">ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED</a>&#160;&#160;&#160;0x0298</td></tr>
<tr class="memdesc:ga627920bebd935709655687d844848934"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned noncontiguous load or store instruction architecturally executed.  <a href="#ga627920bebd935709655687d844848934">More...</a><br/></td></tr>
<tr class="separator:ga627920bebd935709655687d844848934"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC</a>&#160;&#160;&#160;0x0299</td></tr>
<tr class="memdesc:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE unaligned noncontiguous load or store instruction speculatively executed.  <a href="#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">More...</a><br/></td></tr>
<tr class="separator:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9546b924daa3c62e5f117026de58ad94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9546b924daa3c62e5f117026de58ad94">ARM_PMU_MVE_VREDUCE_RETIRED</a>&#160;&#160;&#160;0x02A0</td></tr>
<tr class="memdesc:ga9546b924daa3c62e5f117026de58ad94"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE vector reduction instruction architecturally executed.  <a href="#ga9546b924daa3c62e5f117026de58ad94">More...</a><br/></td></tr>
<tr class="separator:ga9546b924daa3c62e5f117026de58ad94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac714f988ae45871b2865f82c11383b36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac714f988ae45871b2865f82c11383b36">ARM_PMU_MVE_VREDUCE_SPEC</a>&#160;&#160;&#160;0x02A1</td></tr>
<tr class="memdesc:gac714f988ae45871b2865f82c11383b36"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE vector reduction instruction speculatively executed.  <a href="#gac714f988ae45871b2865f82c11383b36">More...</a><br/></td></tr>
<tr class="separator:gac714f988ae45871b2865f82c11383b36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77fad5ad424271ed63fec98af071bb79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga77fad5ad424271ed63fec98af071bb79">ARM_PMU_MVE_VREDUCE_FP_RETIRED</a>&#160;&#160;&#160;0x02A4</td></tr>
<tr class="memdesc:ga77fad5ad424271ed63fec98af071bb79"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE floating-point vector reduction instruction architecturally executed.  <a href="#ga77fad5ad424271ed63fec98af071bb79">More...</a><br/></td></tr>
<tr class="separator:ga77fad5ad424271ed63fec98af071bb79"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa07c698f58c622d234a0007249717265"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa07c698f58c622d234a0007249717265">ARM_PMU_MVE_VREDUCE_FP_SPEC</a>&#160;&#160;&#160;0x02A5</td></tr>
<tr class="memdesc:gaa07c698f58c622d234a0007249717265"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE floating-point vector reduction instruction speculatively executed.  <a href="#gaa07c698f58c622d234a0007249717265">More...</a><br/></td></tr>
<tr class="separator:gaa07c698f58c622d234a0007249717265"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga649e7e81f0fd04ca6611f6a6c4035c57">ARM_PMU_MVE_VREDUCE_INT_RETIRED</a>&#160;&#160;&#160;0x02A8</td></tr>
<tr class="memdesc:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE integer vector reduction instruction architecturally executed.  <a href="#ga649e7e81f0fd04ca6611f6a6c4035c57">More...</a><br/></td></tr>
<tr class="separator:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b6f0bcfd63207c7bab03ea20167dd4b">ARM_PMU_MVE_VREDUCE_INT_SPEC</a>&#160;&#160;&#160;0x02A9</td></tr>
<tr class="memdesc:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">MVE integer vector reduction instruction speculatively executed.  <a href="#ga5b6f0bcfd63207c7bab03ea20167dd4b">More...</a><br/></td></tr>
<tr class="separator:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga01b4792990494b8f084ee00933a1adb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga01b4792990494b8f084ee00933a1adb0">ARM_PMU_MVE_PRED</a>&#160;&#160;&#160;0x02B8</td></tr>
<tr class="memdesc:ga01b4792990494b8f084ee00933a1adb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cycles where one or more predicated beats architecturally executed.  <a href="#ga01b4792990494b8f084ee00933a1adb0">More...</a><br/></td></tr>
<tr class="separator:ga01b4792990494b8f084ee00933a1adb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2a45ec75b2011bd8375d89b7562b2de6">ARM_PMU_MVE_STALL</a>&#160;&#160;&#160;0x02CC</td></tr>
<tr class="memdesc:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction.  <a href="#ga2a45ec75b2011bd8375d89b7562b2de6">More...</a><br/></td></tr>
<tr class="separator:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8f4949084efce03d09bf5ba74cc91edd">ARM_PMU_MVE_STALL_RESOURCE</a>&#160;&#160;&#160;0x02CD</td></tr>
<tr class="memdesc:ga8f4949084efce03d09bf5ba74cc91edd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of resource conflicts.  <a href="#ga8f4949084efce03d09bf5ba74cc91edd">More...</a><br/></td></tr>
<tr class="separator:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab486f5753edd9f10b0f100ff78944dd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab486f5753edd9f10b0f100ff78944dd3">ARM_PMU_MVE_STALL_RESOURCE_MEM</a>&#160;&#160;&#160;0x02CE</td></tr>
<tr class="memdesc:gab486f5753edd9f10b0f100ff78944dd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of memory resource conflicts.  <a href="#gab486f5753edd9f10b0f100ff78944dd3">More...</a><br/></td></tr>
<tr class="separator:gab486f5753edd9f10b0f100ff78944dd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7e76060791618f9b4d49ad493cfb6ba9">ARM_PMU_MVE_STALL_RESOURCE_FP</a>&#160;&#160;&#160;0x02CF</td></tr>
<tr class="memdesc:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of floating-point resource conflicts.  <a href="#ga7e76060791618f9b4d49ad493cfb6ba9">More...</a><br/></td></tr>
<tr class="separator:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaef33b3ff7f12d31238ff4dded5e67a11">ARM_PMU_MVE_STALL_RESOURCE_INT</a>&#160;&#160;&#160;0x02D0</td></tr>
<tr class="memdesc:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of integer resource conflicts.  <a href="#gaef33b3ff7f12d31238ff4dded5e67a11">More...</a><br/></td></tr>
<tr class="separator:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9a1cfef96ec7cd70acf134e368d8826a">ARM_PMU_MVE_STALL_BREAK</a>&#160;&#160;&#160;0x02D3</td></tr>
<tr class="memdesc:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE chain break.  <a href="#ga9a1cfef96ec7cd70acf134e368d8826a">More...</a><br/></td></tr>
<tr class="separator:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga29bc4c2e820914e94e2eb68a6a3352b9">ARM_PMU_MVE_STALL_DEPENDENCY</a>&#160;&#160;&#160;0x02D4</td></tr>
<tr class="memdesc:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by MVE register dependency.  <a href="#ga29bc4c2e820914e94e2eb68a6a3352b9">More...</a><br/></td></tr>
<tr class="separator:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237">ARM_PMU_ITCM_ACCESS</a>&#160;&#160;&#160;0x4007</td></tr>
<tr class="memdesc:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction TCM access.  <a href="#gaf23d758fe1a4cfe6f114cb3e78709237">More...</a><br/></td></tr>
<tr class="separator:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403">ARM_PMU_DTCM_ACCESS</a>&#160;&#160;&#160;0x4008</td></tr>
<tr class="memdesc:ga74aaa0fa0571f74168ee9608d5a02403"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data TCM access.  <a href="#ga74aaa0fa0571f74168ee9608d5a02403">More...</a><br/></td></tr>
<tr class="separator:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadaa75dc2ccfbf7a2263da9a9011f1603">ARM_PMU_TRCEXTOUT0</a>&#160;&#160;&#160;0x4010</td></tr>
<tr class="memdesc:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 0.  <a href="#gadaa75dc2ccfbf7a2263da9a9011f1603">More...</a><br/></td></tr>
<tr class="separator:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga47fe03fe6fe9bfebd98283cb57d94560">ARM_PMU_TRCEXTOUT1</a>&#160;&#160;&#160;0x4011</td></tr>
<tr class="memdesc:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 1.  <a href="#ga47fe03fe6fe9bfebd98283cb57d94560">More...</a><br/></td></tr>
<tr class="separator:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab80e47ffebc3ae6ed2952756b020dbb9">ARM_PMU_TRCEXTOUT2</a>&#160;&#160;&#160;0x4012</td></tr>
<tr class="memdesc:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 2.  <a href="#gab80e47ffebc3ae6ed2952756b020dbb9">More...</a><br/></td></tr>
<tr class="separator:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad70a3b074efd967485ffbfd3e387051d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad70a3b074efd967485ffbfd3e387051d">ARM_PMU_TRCEXTOUT3</a>&#160;&#160;&#160;0x4013</td></tr>
<tr class="memdesc:gad70a3b074efd967485ffbfd3e387051d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 3.  <a href="#gad70a3b074efd967485ffbfd3e387051d">More...</a><br/></td></tr>
<tr class="separator:gad70a3b074efd967485ffbfd3e387051d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga290974d72b8cac214f4e9a152ca64a56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56">ARM_PMU_CTI_TRIGOUT4</a>&#160;&#160;&#160;0x4018</td></tr>
<tr class="memdesc:ga290974d72b8cac214f4e9a152ca64a56"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 4.  <a href="#ga290974d72b8cac214f4e9a152ca64a56">More...</a><br/></td></tr>
<tr class="separator:ga290974d72b8cac214f4e9a152ca64a56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2">ARM_PMU_CTI_TRIGOUT5</a>&#160;&#160;&#160;0x4019</td></tr>
<tr class="memdesc:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 5.  <a href="#ga7a05420b7fae6f5c3d35e12a9846c7e2">More...</a><br/></td></tr>
<tr class="separator:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b">ARM_PMU_CTI_TRIGOUT6</a>&#160;&#160;&#160;0x401A</td></tr>
<tr class="memdesc:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 6.  <a href="#gade076a5ee512a14f8882d9aec5d3dc0b">More...</a><br/></td></tr>
<tr class="separator:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488">ARM_PMU_CTI_TRIGOUT7</a>&#160;&#160;&#160;0x401B</td></tr>
<tr class="memdesc:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 7.  <a href="#ga4388c85b636bd71b4ee1a03b6e96c488">More...</a><br/></td></tr>
<tr class="separator:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>IDs for Armv8.1-M architecture defined events. </p>
<p>These events are available on all Armv8.1-M devices including a PMU. </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gaf2e0a38b7c0d63d1194f08478781a3f0"></a>
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          <td class="memname">#define ARM_PMU_BF_CANCEL&#160;&#160;&#160;0x0109</td>
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      </table>
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<p>Branch future instruction not taken. </p>

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          <td class="memname">#define ARM_PMU_BF_RETIRED&#160;&#160;&#160;0x0104</td>
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<p>Branch future instruction architecturally executed and condition code check pass. </p>

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<a class="anchor" id="ga6b1e4823d8b45678a29a5f54b859d4e3"></a>
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          <td class="memname">#define ARM_PMU_BF_SPEC&#160;&#160;&#160;0x0105</td>
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<p>Branch future instruction speculatively executed and condition code check pass. </p>

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<a class="anchor" id="ga22bfb189fff7c1ea9f81097a543ed756"></a>
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          <td class="memname">#define ARM_PMU_BR_IMMED_RETIRED&#160;&#160;&#160;0x000D</td>
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<p>Immediate branch architecturally executed. </p>

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          <td class="memname">#define ARM_PMU_BR_MIS_PRED&#160;&#160;&#160;0x0010</td>
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<p>Mispredicted or not predicted branch speculatively executed. </p>

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      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_BR_MIS_PRED_RETIRED&#160;&#160;&#160;0x0022</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Mispredicted branch instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga60ccf42eae576e2fde3b9e17a8defeaa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_BR_PRED&#160;&#160;&#160;0x0012</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Predictable branch speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gab3b505a8bcc2b2885626d2f2cd542b73"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_BR_RETIRED&#160;&#160;&#160;0x0021</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Branch instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gab717347b1c3601cffb9c99b43b2a45c5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_BR_RETURN_RETIRED&#160;&#160;&#160;0x000E</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Function return instruction architecturally executed and the condition code check pass. </p>

</div>
</div>
<a class="anchor" id="gaa681d3db56b42775093869b8fdf1abb9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_BUS_ACCESS&#160;&#160;&#160;0x0019</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bus access. </p>

</div>
</div>
<a class="anchor" id="gae4c955416707f44f066ffd2560b9ae4c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_BUS_CYCLES&#160;&#160;&#160;0x001D</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bus cycles. </p>

</div>
</div>
<a class="anchor" id="gaca14907c5a1e1f9915159bc4cf323cf0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_CHAIN&#160;&#160;&#160;0x001E</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE. </p>

</div>
</div>
<a class="anchor" id="ga550d524d435a653b2f46acc1380a5ace"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_CPU_CYCLES&#160;&#160;&#160;0x0011</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cycle. </p>

</div>
</div>
<a class="anchor" id="ga290974d72b8cac214f4e9a152ca64a56"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_CTI_TRIGOUT4&#160;&#160;&#160;0x4018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cross-trigger Interface output trigger 4. </p>

</div>
</div>
<a class="anchor" id="ga7a05420b7fae6f5c3d35e12a9846c7e2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_CTI_TRIGOUT5&#160;&#160;&#160;0x4019</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cross-trigger Interface output trigger 5. </p>

</div>
</div>
<a class="anchor" id="gade076a5ee512a14f8882d9aec5d3dc0b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_CTI_TRIGOUT6&#160;&#160;&#160;0x401A</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cross-trigger Interface output trigger 6. </p>

</div>
</div>
<a class="anchor" id="ga4388c85b636bd71b4ee1a03b6e96c488"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_CTI_TRIGOUT7&#160;&#160;&#160;0x401B</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cross-trigger Interface output trigger 7. </p>

</div>
</div>
<a class="anchor" id="ga74aaa0fa0571f74168ee9608d5a02403"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_DTCM_ACCESS&#160;&#160;&#160;0x4008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data TCM access. </p>

</div>
</div>
<a class="anchor" id="ga18d640aa04b97c7d287e8745f6f2b23d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_DWT_CMPMATCH0&#160;&#160;&#160;0x0118</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DWT comparator 0 match. </p>

</div>
</div>
<a class="anchor" id="ga5dc6eb2be1ff1afe9cbd59af4f6078ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_DWT_CMPMATCH1&#160;&#160;&#160;0x0119</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DWT comparator 1 match. </p>

</div>
</div>
<a class="anchor" id="ga58a4815dba8886088b9cac7b934a332d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_DWT_CMPMATCH2&#160;&#160;&#160;0x011A</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DWT comparator 2 match. </p>

</div>
</div>
<a class="anchor" id="ga594337c6f3c88d8317203a8cd6f9814a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_DWT_CMPMATCH3&#160;&#160;&#160;0x011B</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DWT comparator 3 match. </p>

</div>
</div>
<a class="anchor" id="gaf9424157e9c5dca3a3689d181005c4f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_EXC_RETURN&#160;&#160;&#160;0x000A</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Exception return instruction architecturally executed and the condition code check pass. </p>

</div>
</div>
<a class="anchor" id="gac97858bd621eab4592569444f0a5c37f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_EXC_TAKEN&#160;&#160;&#160;0x0009</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Exception entry. </p>

</div>
</div>
<a class="anchor" id="ga8a5e60eee460addfc66e275a2c4c4800"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_INST_RETIRED&#160;&#160;&#160;0x0008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaf7bad54617ace5c2fb48bc2e8aebf9c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_INST_SPEC&#160;&#160;&#160;0x001B</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gaf23d758fe1a4cfe6f114cb3e78709237"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_ITCM_ACCESS&#160;&#160;&#160;0x4007</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Instruction TCM access. </p>

</div>
</div>
<a class="anchor" id="ga7505ae74c1d905f01b05dd5466c1efc0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1D_CACHE&#160;&#160;&#160;0x0004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>L1 D-Cache access. </p>

</div>
</div>
<a class="anchor" id="gab55334c8510cb30c4c750913f6eb6279"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1D_CACHE_ALLOCATE&#160;&#160;&#160;0x001F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 1 data cache allocation without refill. </p>

</div>
</div>
<a class="anchor" id="ga4687d5d7efc6f49db2db9acc25b590f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1D_CACHE_MISS_RD&#160;&#160;&#160;0x0039</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 1 data cache read miss. </p>

</div>
</div>
<a class="anchor" id="gaf4236dfbcb4550d3cc98caee837e8e77"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1D_CACHE_RD&#160;&#160;&#160;0x0040</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 1 data cache read. </p>

</div>
</div>
<a class="anchor" id="ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1D_CACHE_REFILL&#160;&#160;&#160;0x0003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>L1 D-Cache refill. </p>

</div>
</div>
<a class="anchor" id="ga27d1b8b2c37ae0ae41781880ed3893d0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1D_CACHE_WB&#160;&#160;&#160;0x0015</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 1 data cache write-back. </p>

</div>
</div>
<a class="anchor" id="gaf8e89b2b098e6bec5916517346925ce2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1I_CACHE&#160;&#160;&#160;0x0014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 1 instruction cache access. </p>

</div>
</div>
<a class="anchor" id="gac43e0e0f9e385ea66402bdeebf3fea3e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L1I_CACHE_REFILL&#160;&#160;&#160;0x0001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>L1 I-Cache refill. </p>

</div>
</div>
<a class="anchor" id="gafb1e1f86d091ccb735858769c700e289"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L2D_CACHE&#160;&#160;&#160;0x0016</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 2 data cache access. </p>

</div>
</div>
<a class="anchor" id="gaad08dcded491bf257d223e4171af41cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L2D_CACHE_ALLOCATE&#160;&#160;&#160;0x0020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 2 data cache allocation without refill. </p>

</div>
</div>
<a class="anchor" id="gaeb414c1b0375022abc2502ab503a3284"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L2D_CACHE_REFILL&#160;&#160;&#160;0x0017</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 2 data cache refill. </p>

</div>
</div>
<a class="anchor" id="ga1a0c4a1990eeed88edc3e1e0c4b1aca0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L2D_CACHE_WB&#160;&#160;&#160;0x0018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 2 data cache write-back. </p>

</div>
</div>
<a class="anchor" id="ga3406498b2c17ca080ebd68cc40d9630e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L2I_CACHE&#160;&#160;&#160;0x0027</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 2 instruction cache access. </p>

</div>
</div>
<a class="anchor" id="gaa18cee03802b46076e9ab66fd0a7c61d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L2I_CACHE_REFILL&#160;&#160;&#160;0x0028</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 2 instruction cache refill. </p>

</div>
</div>
<a class="anchor" id="ga4e96b5a6fb13c657e78da342a02db200"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L3D_CACHE&#160;&#160;&#160;0x002B</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 3 data cache access. </p>

</div>
</div>
<a class="anchor" id="gac11cbc6849dbad7bd8b64ab6e2a3f8d5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L3D_CACHE_ALLOCATE&#160;&#160;&#160;0x0029</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 3 data cache allocation without refill. </p>

</div>
</div>
<a class="anchor" id="gafe99db0693125100272247c147fb3b02"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L3D_CACHE_REFILL&#160;&#160;&#160;0x002A</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 3 data cache refill. </p>

</div>
</div>
<a class="anchor" id="gab823f95f7ac8196a208d12381b1b2a11"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_L3D_CACHE_WB&#160;&#160;&#160;0x002C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Level 3 data cache write-back. </p>

</div>
</div>
<a class="anchor" id="ga2e8725ee07c2b2c75a1b54261bc26cc8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_LD_RETIRED&#160;&#160;&#160;0x0006</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Memory-reading instruction architecturally executed and condition code check pass. </p>

</div>
</div>
<a class="anchor" id="ga8b5641a3cb0e922a2b4e16ec14052861"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_LE_CANCEL&#160;&#160;&#160;0x0108</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Loop end instruction not taken. </p>

</div>
</div>
<a class="anchor" id="ga345461506c990125b1f2cbc62e3be22f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_LE_RETIRED&#160;&#160;&#160;0x0100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Loop end instruction executed. </p>

</div>
</div>
<a class="anchor" id="ga6a1d9f84bda091e96843665ff3913b50"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_LE_SPEC&#160;&#160;&#160;0x0101</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Loop end instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga6979efa69af7d0e62cc3e2f88b0155b8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_LL_CACHE_MISS_RD&#160;&#160;&#160;0x0037</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Last level data cache read miss. </p>

</div>
</div>
<a class="anchor" id="ga902562d8161fffd45726dc4cc8727545"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_LL_CACHE_RD&#160;&#160;&#160;0x0036</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Last level data cache read. </p>

</div>
</div>
<a class="anchor" id="gab3852c2b3d59af106b9db7ea2c20c367"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MEM_ACCESS&#160;&#160;&#160;0x0013</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data memory access. </p>

</div>
</div>
<a class="anchor" id="ga2c8d23cc64e87b2044bb39bf8d0bc1b1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MEMORY_ERROR&#160;&#160;&#160;0x001A</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Local memory error. </p>

</div>
</div>
<a class="anchor" id="gaa4c408a006a04e95ade26922669b6695"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_HP_RETIRED&#160;&#160;&#160;0x0208</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE half-precision floating-point instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaf01d187b0cbf418d1fac55dd0ddd0827"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_HP_SPEC&#160;&#160;&#160;0x0209</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE half-precision floating-point instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gac2dc7d92627b3caa391725a3f080288c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_MAC_RETIRED&#160;&#160;&#160;0x0214</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE floating-point multiply or multiply-accumulate instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaf5302b3278a862c9264171955328a59a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_MAC_SPEC&#160;&#160;&#160;0x0215</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE floating-point multiply or multiply-accumulate instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga268b0bcbd30e8a928bd0f331fdf53ccf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_RETIRED&#160;&#160;&#160;0x0204</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE floating-point instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gab21171c50ebd1f304b11260edd015f52"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_SP_RETIRED&#160;&#160;&#160;0x020C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE single-precision floating-point instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gae69e310892661af852ca2d4ec947d18a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_SP_SPEC&#160;&#160;&#160;0x020D</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE single-precision floating-point instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gadf9cfd45b59acfc314ebc814a1bcdccd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_FP_SPEC&#160;&#160;&#160;0x0205</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE floating-point instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga3c1006bed2fb82b0749386261b397727"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_INST_RETIRED&#160;&#160;&#160;0x0200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga1e276b6872345eb3b043626a11f235c6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_INST_SPEC&#160;&#160;&#160;0x0201</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga9248c93a3f19fddc93d3804a06f7238a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_INT_MAC_RETIRED&#160;&#160;&#160;0x0228</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE multiply or multiply-accumulate instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga7036f00faa9183ae450a3e4d9d6f2bbf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_INT_MAC_SPEC&#160;&#160;&#160;0x0229</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE multiply or multiply-accumulate instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga5e3afafa91ebaeac0469a19ebb54719c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_INT_RETIRED&#160;&#160;&#160;0x0224</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE integer instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga16ed0bb1bb4718da93c41238da652d33"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_INT_SPEC&#160;&#160;&#160;0x0225</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE integer instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga8732a737f2b7adc43e3d1da7b3da92e6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_RETIRED&#160;&#160;&#160;0x0248</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE contiguous load instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga8e58fe07254256fa3bf3d42fa2062141"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_SPEC&#160;&#160;&#160;0x0249</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE contiguous load instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga50fb13c874b3f5e2b9ed9c320a36452c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_MULTI_RETIRED&#160;&#160;&#160;0x0260</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE memory load instruction targeting multiple registers architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaf2d4e3d1f06d97899de7fa791477d62b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_MULTI_SPEC&#160;&#160;&#160;0x0261</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE memory load instruction targeting multiple registers speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gaaf2ce8c0ea4c03c934aac6afc31fc5ff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED&#160;&#160;&#160;0x0254</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE non-contiguous load instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gadbcb82b7924b7bbee5c0d42a3de38572"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_SPEC&#160;&#160;&#160;0x0255</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE non-contiguous load instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gaa3379a51350a2fda8d8ab6d7795baa7a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_RETIRED&#160;&#160;&#160;0x023C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE load instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga78a6f89ab30ed01f7d8388eda697b4f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_SPEC&#160;&#160;&#160;0x023D</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE load instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga26ed05deaa7b993904300069f0ecfac4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED&#160;&#160;&#160;0x0290</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned load instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gadc3bd0f32e0a08bba2d533479a59bd6e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_SPEC&#160;&#160;&#160;0x0291</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned load instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga8acf6a66c63798b76608caf52c96658d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_RETIRED&#160;&#160;&#160;0x0244</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE contiguous load or store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga5a83ef6a52739e1d223be503bbdaaab6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_SPEC&#160;&#160;&#160;0x0245</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE contiguous load or store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga7d669378441408fc21aa551e483866cb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_RETIRED&#160;&#160;&#160;0x025C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE memory instruction targeting multiple registers architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga7ea46cde08cb0cc4a46ef23835fb5aac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_SPEC&#160;&#160;&#160;0x025D</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE memory instruction targeting multiple registers speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga7065b7f0aea461858b72912d22c329f2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED&#160;&#160;&#160;0x0250</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE non-contiguous load or store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga193605eb52709741d91a64e3ad1a5894"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC&#160;&#160;&#160;0x0251</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE non-contiguous load or store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga7d7d465a6c64400c49f93b6c8152296f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_RETIRED&#160;&#160;&#160;0x0238</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE load or store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaa98a18c06bd13daf2df6f89219ec68d5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_SPEC&#160;&#160;&#160;0x0239</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE load or store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga627920bebd935709655687d844848934"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED&#160;&#160;&#160;0x0298</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned noncontiguous load or store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaf9ebeb1f49dba56d8f90f9bd5d3da58e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC&#160;&#160;&#160;0x0299</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned noncontiguous load or store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gaf358a9ed5c83a10cb695d9b19b1b3bc1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED&#160;&#160;&#160;0x028C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned memory load or store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gab2264786bed578c89109859b55909c76"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC&#160;&#160;&#160;0x028D</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned memory load or store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga01b4792990494b8f084ee00933a1adb0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_PRED&#160;&#160;&#160;0x02B8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cycles where one or more predicated beats architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gacb3c0b922eae9aac321df97ec889e0ed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_RETIRED&#160;&#160;&#160;0x024C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE contiguous store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga02cd64b9444e4babc7b69e8571d39bdd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_SPEC&#160;&#160;&#160;0x024D</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE contiguous store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga76057cbda353b4ad6fbc3b6a63c193a5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_MULTI_RETIRED&#160;&#160;&#160;0x0261</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE memory store instruction targeting multiple registers architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaf6a14402c79dba8fa765e8663dd0734d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_MULTI_SPEC&#160;&#160;&#160;0x0265</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE memory store instruction targeting multiple registers speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga8271f415ecc7573b57e82a24aec86ef1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED&#160;&#160;&#160;0x0258</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE non-contiguous store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga059327c80f396918a9f8192bcd0fa4a8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_SPEC&#160;&#160;&#160;0x0259</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE non-contiguous store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="gad8d0079977fa97de4ee263703f1b2908"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_RETIRED&#160;&#160;&#160;0x0240</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gabd3984d299b5416aac8d630722680c55"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_SPEC&#160;&#160;&#160;0x0241</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga391afd8cb92cc65161b13ee3a3256d40"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED&#160;&#160;&#160;0x0294</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned store instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="ga21bf105499df85196b4137cb075a6fbe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_SPEC&#160;&#160;&#160;0x0295</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE unaligned store instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga2a45ec75b2011bd8375d89b7562b2de6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL&#160;&#160;&#160;0x02CC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by an MVE instruction. </p>

</div>
</div>
<a class="anchor" id="ga9a1cfef96ec7cd70acf134e368d8826a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL_BREAK&#160;&#160;&#160;0x02D3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by an MVE chain break. </p>

</div>
</div>
<a class="anchor" id="ga29bc4c2e820914e94e2eb68a6a3352b9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL_DEPENDENCY&#160;&#160;&#160;0x02D4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by MVE register dependency. </p>

</div>
</div>
<a class="anchor" id="ga8f4949084efce03d09bf5ba74cc91edd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE&#160;&#160;&#160;0x02CD</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by an MVE instruction because of resource conflicts. </p>

</div>
</div>
<a class="anchor" id="ga7e76060791618f9b4d49ad493cfb6ba9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_FP&#160;&#160;&#160;0x02CF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by an MVE instruction because of floating-point resource conflicts. </p>

</div>
</div>
<a class="anchor" id="gaef33b3ff7f12d31238ff4dded5e67a11"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_INT&#160;&#160;&#160;0x02D0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by an MVE instruction because of integer resource conflicts. </p>

</div>
</div>
<a class="anchor" id="gab486f5753edd9f10b0f100ff78944dd3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_MEM&#160;&#160;&#160;0x02CE</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycles caused by an MVE instruction because of memory resource conflicts. </p>

</div>
</div>
<a class="anchor" id="ga77fad5ad424271ed63fec98af071bb79"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_RETIRED&#160;&#160;&#160;0x02A4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE floating-point vector reduction instruction architecturally executed. </p>

</div>
</div>
<a class="anchor" id="gaa07c698f58c622d234a0007249717265"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_SPEC&#160;&#160;&#160;0x02A5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MVE floating-point vector reduction instruction speculatively executed. </p>

</div>
</div>
<a class="anchor" id="ga649e7e81f0fd04ca6611f6a6c4035c57"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_RETIRED&#160;&#160;&#160;0x02A8</td>
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<p>MVE integer vector reduction instruction architecturally executed. </p>

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<a class="anchor" id="ga5b6f0bcfd63207c7bab03ea20167dd4b"></a>
<div class="memitem">
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          <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_SPEC&#160;&#160;&#160;0x02A9</td>
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      </table>
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<p>MVE integer vector reduction instruction speculatively executed. </p>

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<a class="anchor" id="ga9546b924daa3c62e5f117026de58ad94"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_MVE_VREDUCE_RETIRED&#160;&#160;&#160;0x02A0</td>
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<p>MVE vector reduction instruction architecturally executed. </p>

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<a class="anchor" id="gac714f988ae45871b2865f82c11383b36"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_MVE_VREDUCE_SPEC&#160;&#160;&#160;0x02A1</td>
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<p>MVE vector reduction instruction speculatively executed. </p>

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<a class="anchor" id="ga2fe9d3ea67ce833bd6323e4ce1a4e894"></a>
<div class="memitem">
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          <td class="memname">#define ARM_PMU_OP_COMPLETE&#160;&#160;&#160;0x003A</td>
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<p>Operation retired. </p>

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<a class="anchor" id="ga6c59149e9b1754987b44b62092bc9f09"></a>
<div class="memitem">
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          <td class="memname">#define ARM_PMU_OP_SPEC&#160;&#160;&#160;0x003B</td>
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<p>Operation speculatively executed. </p>

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<a class="anchor" id="ga54fd2c392399221077c67866a395e587"></a>
<div class="memitem">
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          <td class="memname">#define ARM_PMU_PC_WRITE_RETIRED&#160;&#160;&#160;0x000C</td>
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<p>Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass. </p>

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<a class="anchor" id="gaaae2c32a8ecd36b59ac98cf8e23b3cab"></a>
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          <td class="memname">#define ARM_PMU_SE_CALL_NS&#160;&#160;&#160;0x0115</td>
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<p>Call to non-secure function, resulting in Security state change. </p>

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<a class="anchor" id="gad3ba2effbe303ca3fafdbc022fe206c1"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_SE_CALL_S&#160;&#160;&#160;0x0114</td>
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</div><div class="memdoc">

<p>Call to secure function, resulting in Security state change. </p>

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<a class="anchor" id="ga8179d1144f8ec993bd1343e276d7b49b"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_ST_RETIRED&#160;&#160;&#160;0x0007</td>
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<p>Memory-writing instruction architecturally executed and condition code check pass. </p>

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<a class="anchor" id="ga8bf75efa06a125ee2dfa9a130e7ba9a8"></a>
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<div class="memproto">
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          <td class="memname">#define ARM_PMU_STALL&#160;&#160;&#160;0x003C</td>
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<p>Stall cycle for instruction or operation not sent for execution. </p>

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<a class="anchor" id="ga8737bee352820bd7d1bc8e5e4260143c"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_STALL_BACKEND&#160;&#160;&#160;0x0024</td>
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      </table>
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<p>No operation issued because of the backend. </p>

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<a class="anchor" id="ga5b068593baa831348664dfa7d44f5483"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_STALL_FRONTEND&#160;&#160;&#160;0x0023</td>
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<p>No operation issued because of the frontend. </p>

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<a class="anchor" id="ga197b491f691110fb52aef4291782b6ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define ARM_PMU_STALL_OP&#160;&#160;&#160;0x003F</td>
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</div><div class="memdoc">

<p>Instruction or operation slots not occupied each cycle. </p>

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<a class="anchor" id="ga9700ec74727a9fe3cd4cd40736628a23"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define ARM_PMU_STALL_OP_BACKEND&#160;&#160;&#160;0x003D</td>
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<p>Stall cycle for instruction or operation not sent for execution due to pipeline backend. </p>

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</div>
<a class="anchor" id="ga69cfd3558cf6c6f3bb621ee75430427c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_STALL_OP_FRONTEND&#160;&#160;&#160;0x003E</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stall cycle for instruction or operation not sent for execution due to pipeline frontend. </p>

</div>
</div>
<a class="anchor" id="ga6e02b08550d7e9b273ff7913f1b57bea"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define ARM_PMU_SW_INCR&#160;&#160;&#160;0x0000</td>
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</div><div class="memdoc">

<p>Software update to the PMU_SWINC register, architecturally executed and condition code check pass. </p>

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</div>
<a class="anchor" id="gadaa75dc2ccfbf7a2263da9a9011f1603"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define ARM_PMU_TRCEXTOUT0&#160;&#160;&#160;0x4010</td>
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      </table>
</div><div class="memdoc">

<p>ETM external output 0. </p>

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</div>
<a class="anchor" id="ga47fe03fe6fe9bfebd98283cb57d94560"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_TRCEXTOUT1&#160;&#160;&#160;0x4011</td>
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</div><div class="memdoc">

<p>ETM external output 1. </p>

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</div>
<a class="anchor" id="gab80e47ffebc3ae6ed2952756b020dbb9"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define ARM_PMU_TRCEXTOUT2&#160;&#160;&#160;0x4012</td>
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</div><div class="memdoc">

<p>ETM external output 2. </p>

</div>
</div>
<a class="anchor" id="gad70a3b074efd967485ffbfd3e387051d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define ARM_PMU_TRCEXTOUT3&#160;&#160;&#160;0x4013</td>
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</div><div class="memdoc">

<p>ETM external output 3. </p>

</div>
</div>
<a class="anchor" id="ga45d5ea86fdc015f4fc100462150c92da"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define ARM_PMU_UNALIGNED_LDST_RETIRED&#160;&#160;&#160;0x000F</td>
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      </table>
</div><div class="memdoc">

<p>Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass. </p>

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